hsmp-382x, 482x surface mount rf pin switch and limiter diodes data sheet features ? diodes optimized for: low current switching low distortion attenuating ? power limiting /circuit protection ? surface mount sot-23 and sot-323 packages single and dual versions tape and reel options available ? low failure in time (fit) rate [1] ? lead-free note: 1. for more information see the surface mount pin reliability data sheet. package lead code identifi cation, sot-323 (top view) description/applications the hsmp-382x series is optimized for switch ing ap- plications where ultra-low resistance is required. the hsmp-482x diode is ideal for limiting and low induc- tance switching applications up to 1.5 ghz. a spice model is not available for pin diodes as spice does not provide for a key pin diode characteristic, carrier lifetime. package lead code identifi cation, sot-23 (top view) common cathode #4 common anode #3 series #2 single #0 dual anode hsmp-4820 dual anode hsmp-482b
2 absolute maximum ratings [1] t c = +25c symbol parameter unit sot-23 sot-323 i f forward current (1 s pulse) amp 1 1 p iv peak inverse voltage v 50 50 t j junction temperature c 150 150 t stg storage temperature c -65 to 150 -65 to 150 jc thermal resistance [2] c/w 500 150 notes: 1. operation in excess of any one of these conditions may result in permanent damage to the device. 2. t c = +25c, where t c is defi ned to be the temperature at the package pins where contact is made to the circuit board. minimum maximum typical maximum typical part package breakdown series total total total number marking lead voltage resistance capacitance capacitance inductance hsmp- code code confi guration v br (v) r s () c t (pf) c t (pf) l t (nh) 4820 fa a dual anode 50 0.6 0.75 1.2 1.0 482b fa a dual anode test conditions v r = v br i f = 10 ma f = 1 mhz f = 1 mhz f = 500 mhz C measure v r = 20 v v r = 0 v 3 ghz i r 10 a high frequency (low inductance, 500 mhz C 3 ghz) pin diodes electrical specifi cations t c = 25c package minimum maximum maximum part number marking lead breakdown series resistance total capacitance hsmp- code code confi guration voltage v br (v) r s () c t (pf) 3820 f0 0 single 50 0.6 0.8 3822 f2 2 series 3823 f3 3 common anode 3824 f4 4 common cathode test conditions v r = v br f = 100 mhz f = 1 mhz measure i f = 10 ma v r = 20 v i r 10 a typical parameters at t c = 25c part number series resistance carrier lifetime reverse recovery time total capacitance hsmp- r s () (ns) t rr (ns) c t (pf) 382x 1.5 70 7 0.60 @ 20 v test conditions f = 100 mhz i f = 10 ma v r = 10 v i f = 10 ma i f = 20 ma 90% recovery
3 typical parameters at t c = 25c (unless otherwise noted), single diode figure 3. rf resistance at 25c vs. forward bias current. 100 10 1 0.1 rf resistance (ohms) i f C forward bias current (ma) 0.01 0.1 1 10 100 1.4 1.2 1.0 0.8 0.6 0 1020304050 v r C reverse voltage (v) capacitance (pf) figure 4. capacitance vs. reverse voltage. 120 115 110 105 100 95 90 85 11030 i f C forward bias current (ma) figure 5. 2nd harmonic input intercept point vs. forward bias current. input intercept point (dbm) diode mounted as a series attenuator in a 50 ohm microstrip and tested at 123 mhz forward current (ma) figure 2. reverse recovery time vs. forward current for various reverse voltages. t rr C reverse recovery time (ns) 1 10 100 10 20 30 v r = 2v v r = 5v v r = 10v 100 10 1 0.1 0.01 0 0.2 0.4 0.6 0.8 1.0 1.2 i f C forward current (ma) v f C forward voltage (ma) figure 1. forward current vs. forward voltage. 125c 25c C50c cw power in (dbm) figure 6. large signal transfer curve of the hsmp-482x limiter. cw power out (dbm) 0 30 25 20 15 10 5 0 40 10 5 20 25 30 35 15 measured with external bias return 1.0 ghz 1.5 ghz typical applications for multiple diode products rf common rf 1 bias 1 rf 2 bias 2 figure 7. simple spdt switch, using only positive current. figure 8. high isolation spdt switch, dual bias. rf common bias bias rf 2 rf 1
4 typical applications for multiple diode products, continued bias figure 9. switch using both positive and negative bias current. figure 10. very high isolation spdt switch, dual bias. figure 11. high isolation spst switch (repeat cells as requir ed. figure 12. power limiter using hsmp-3822 diode pair. see application note 1050 for details. rf common rf 1 rf 2 bias rf common rf 2 rf 1 bias
5 typical applications for hsmp-482x low inductance series microstrip series connection for hsmp-482x series in order to take full advantage of the low inductance of the hsmp-482x series when using them in series applications, both lead 1 and lead 2 should be connected together, as shown in figure 14. figure 16. equivalent circuit. co-planar waveguide shunt connection for hsmp-482x series co-planar waveguide, with ground on the top side of the printed circuit board, is shown in figure 17. since it eliminates the need for via holes to ground, it off ers lower shunt parasitic inductance and higher maximum attenuation when compared to a microstrip circuit. see an1050 for details. 50 ohm microstrip lines pad connected to ground by two via holes 12 3 0.3 nh 0.3 nh 0.8 pf 1.5 nh 1.5 nh 0.8 pf 0.75 nh figure 13. internal connections. figure 14. circuit layout. microstrip shunt connections for hsmp-482x series in figure 15, the center conductor of the microstrip line is interrupted and leads 1 and 2 of the hsmp-482x diode are placed across the resulting gap. this forces the 0.5 nh lead inductance of leads 1 and 2 to appear as part of a low pass fi lter, reducing the shunt parasitic inductance and increasing the maximum available attenuation. the 0.3 nh of shunt inductance external to the diode is created by the via holes, and is a good estimate for 0.032" thick material. figure 15. circuit layout, hsmp-482x limiter. figure 17. circuit layout. figure 18. equivalent circuit. co-planar waveguide groundplane groundplane center conductor
6 assembly information sot-323 pcb footprint a recommended pcb pad layout for the miniature sot- 323 (sc-70) package is shown in figure 19 (dimensions are in inches). this layout provides ample allowance for package placement by automated assembly equipment without adding parasitics that could impair the performance. 0.026 0.039 0.079 0.022 dimensions in inches 0.039 1 0.039 1 0.079 2.0 0.031 0.8 dimensions in inches mm 0.035 0.9 figure 19. recommended pcb pad layout for avagos sc70 3l/sot-323 products. sot-23 pcb footprint figure 20. recommended pcb pad layout for avagos sot-23 products.
7 smt assembly reliable assembly of surface mount components is a complex process that involves many material, process, and equipment factors, including: method of heating (e.g., ir or vapor phase refl ow, wave soldering, etc.) circuit board material, conductor thickness and pattern, type of solder alloy, and the thermal conductivity and thermal mass of components. components with a low mass, such as the sot-323/-23 package, will reach solder refl ow temperatures faster than those with a greater mass. avagos diodes have been qualifi ed to the time- temperature profi le shown in figure 21. this profi le is representative of an ir refl ow type of surface mount assembly process. after ramping up from room temperature, the circuit board with components attached to it (held in place with solder paste) passes through one or more preheat zones. the preheat zones increase the temperature of the board and components to prevent thermal shock and begin evaporating solvents from the solder paste. the refl ow zone briefl y elevates the temperature suffi ciently to produce a refl ow of the solder. the rates of change of temperature for the ramp-up and cool-down zones are chosen to be low enough to not cause deformation of the board or damage to components due to thermal shock. the maximum temperature in the refl ow zone (t max ) should not exceed 260c. these parameters are typical for a surface mount assembly process for avago diodes. as a general guideline, the circuit board and components should be exposed only to the minimum temperatures and times necessary to achieve a uniform refl ow of solder. figure 21. surface mount assembly profi le. 25 time temperature tp t l tp t l t 25 c to peak ramp-up ts ts min ramp-down preheat critical zone t l to tp ts max lead-free refl ow profi le recommendation (ipc/jedec j-std-020c) refl ow parameter lead-free assembly average ramp-up rate (liquidus temperature (t s(max) to peak) 3c/ second max preheat temperature min (t s(min) ) 150c temperature max (t s(max) ) 200c time (min to max) (t s ) 60-180 seconds ts(max) to tl ramp-up rate 3c/second max time maintained above: temperature (t l ) 217c time (t l ) 60-150 seconds peak temperature (t p ) 260 +0/-5c time within 5 c of actual peak temperature (t p ) 20-40 seconds ramp-down rate 6c/second max time 25 c to peak temperature 8 minutes max note 1: all temperatures refer to topside of the package, measured on the package body surface
8 package characteristics lead material ....................................................... copper (sot-323); alloy 42 (sot-23) lead finish ............................................................................ tin 100% (lead-free option) maximum soldering temperature ............................................... 260c for 5 seconds minimum lead strength .............................................................................. 2 pounds pull typical package inductance ..........................................................................................2 nh typical package capacitance ................................................. 0.08 pf (opposite leads) ordering information specify part number followed by option. for example: hsmp - 382x - xxx bulk or tape and reel option part number; x = lead code surface mount pin option descriptions -blkg = bulk, 100 pcs. per antistatic bag -tr1g = tape and reel, 3000 devices per 7" reel -tr2g = tape and reel, 10,000 devices per 13" reel tape and reeling conforms to electronic industries rs-481, taping of surface mounted components for automated placement. package dimensions outline 23 (sot-23) outline sot-323 (sc-70) e b e2 e1 e1 c e xxx l d a a1 notes: xxx-package marking drawings are not to scale dimensions (mm) min. 0.79 0.000 0.30 0.08 2.73 1.15 0.89 1.78 0.45 2.10 0.45 max. 1.20 0.100 0.54 0.20 3.13 1.50 1.02 2.04 0.60 2.70 0.69 symbol a a1 b c d e1 e e1 e2 e l e b e1 e1 c e xxx l d a a1 notes: xxx-package marking drawings are not to scale dimensions (mm) min. 0.80 0.00 0.15 0.08 1.80 1.10 1.80 0.26 max. 1.00 0.10 0.40 0.25 2.25 1.40 2.40 0.46 symbol a a1 b c d e1 e e1 e l 1.30 typical 0.65 typical
9 tape dimensions and product orientation for outline sot-23 device orientation for outlines sot-23/323 user feed direction cover tape carrier tape reel note: "ab" represents package marking code. "c" represents date code. end view 8 mm 4 mm top view abc abc abc abc 9 max a 0 p p 0 d p 2 e f w d 1 ko 8 max b 0 13.5 max t1 description symbol size (mm) size (inches) length width depth pitch bottom hole diameter a 0 b 0 k 0 p d 1 3.15 0.10 2.77 0.10 1.22 0.10 4.00 0.10 1.00 + 0.05 0.124 0.004 0.109 0.004 0.048 0.004 0.157 0.004 0.039 0.002 cavity diameter pitch position d p 0 e 1.50 + 0.10 4.00 0.10 1.75 0.10 0.059 + 0.004 0.157 0.004 0.069 0.004 perforation width thickness w t1 8.00 + 0.30 C 0.10 0.229 0.013 0.315 + 0.012 C 0.004 0.009 0.0005 carrier tape cavity to perforation (width direction) cavity to perforation (length direction) f p 2 3.50 0.05 2.00 0.05 0.138 0.002 0.079 0.002 distance between centerline
tape dimensions and product orientation for outline sot-323 for product information and a complete list of distributors, please go to our web site: www.avagotech.com avago, avago technologies, and the a logo are trademarks of avago technologies in the united states and other countries. data subject to change. copyright ? 2005-2012 avago technologies. all rights reserved. obsoletes 5989-4026en av02-1395en - april 24, 2012 p p 0 p 2 f w c d 1 d e a 0 an t 1 (carrier tape thickness) t t (cover tape thickness) an b 0 k 0 description symbol size (mm) size (inches) length width depth pitch bottom hole diameter a 0 b 0 k 0 p d 1 2.40 0.10 2.40 0.10 1.20 0.10 4.00 0.10 1.00 + 0.25 0.094 0.004 0.094 0.004 0.047 0.004 0.157 0.004 0.039 + 0.010 cavity diameter pitch position d p 0 e 1.55 0.05 4.00 0.10 1.75 0.10 0.061 0.002 0.157 0.004 0.069 0.004 perforation width thickness w t 1 8.00 0.30 0.254 0.02 0.315 0.012 0.0100 0.0008 carrier tape cavity to perforation (width direction) cavity to perforation (length direction) f p 2 3.50 0.05 2.00 0.05 0.138 0.002 0.079 0.002 distance for sot-323 (sc70-3 lead) an 8c max for sot-363 (sc70-6 lead) 10c max angle width tape thickness c t t 5.4 0.10 0.062 0.001 0.205 0.004 0.0025 0.00004 cover tape
|
